#ifndef _DRV8323S_H
#define _DRV8323S_H

enum {
  DRV8323S_FAULT_STATUS1_REG = 0x00,
  DRV8323S_FAULT_STATUS2_REG = 0x01,
  DRV8323S_DRIVER_CONTROL_REG = 0x02,
  DRV8323S_GATE_DRIVE_HS_REG = 0x03,
  DRV8323S_GATE_DRIVE_LS_REG = 0x04,
  DRV8323S_OCP_CONTROL_REG = 0x05,
  DRV8323S_CSA_CONTROL_REG = 0x06,
};

enum /* 0x00 */ {
  DRV8323S_FAULT_STATUS1_FAULT_MASK = 1 << 10,  /* logic or of all faults */
  DRV8323S_FAULT_STATUS1_VDS_OCP_MASK = 1 << 9, /* vds monitor overcurrent */
  DRV8323S_FAULT_STATUS1_GDF_MASK = 1 << 8,     /* gate drive fault */
  DRV8323S_FAULT_STATUS1_UVLO_MASK = 1 << 7,    /* undervoltage lockout fault */
  DRV8323S_FAULT_STATUS1_OTSD_MASK = 1 << 6,    /* over temperature shutdown */
  DRV8323S_FAULT_STATUS1_VDS_HA_MASK = 1 << 5,  /* overcurrent on FET */
  DRV8323S_FAULT_STATUS1_VDS_LA_MASK = 1 << 4,
  DRV8323S_FAULT_STATUS1_VDS_HB_MASK = 1 << 3,
  DRV8323S_FAULT_STATUS1_VDS_LB_MASK = 1 << 2,
  DRV8323S_FAULT_STATUS1_VDS_HC_MASK = 1 << 1,
  DRV8323S_FAULT_STATUS1_VDS_LC_MASK = 1 << 0,
};

enum /* 0x01 */ {
  DRV8323S_FAULT_STATUS1_SA_OC_MASK = 1 << 10, /* Sense amp OC */
  DRV8323S_FAULT_STATUS1_SB_OC_MASK = 1 << 9,
  DRV8323S_FAULT_STATUS1_SC_OC_MASK = 1 << 8,
  DRV8323S_FAULT_STATUS1_OTW_MASK = 1 << 7,    /* over temp warning */
  DRV8323S_FAULT_STATUS1_CPUV_MASK = 1 << 6,   /* charge pump fault */
  DRV8323S_FAULT_STATUS1_VGS_HA_MASK = 1 << 5, /* FET gate drive failt */
  DRV8323S_FAULT_STATUS1_VGS_LA_MASK = 1 << 4,
  DRV8323S_FAULT_STATUS1_VGS_HB_MASK = 1 << 3,
  DRV8323S_FAULT_STATUS1_VGS_LB_MASK = 1 << 2,
  DRV8323S_FAULT_STATUS1_VGS_HC_MASK = 1 << 1,
  DRV8323S_FAULT_STATUS1_VGS_LC_MASK = 1 << 0,
};

enum /* 0x02 */ {
  DRV8323S_DRIVER_CONTROL_DIS_CPUV_MASK =
      1 << 9, /* chrg pump uvlo fault disable */
  DRV8323S_DRIVER_CONTROL_DIS_GDF_MASK = 1 << 8, /* gate drive fault disable */
  DRV8323S_DRIVER_CONTROL_OTW_REP_MASK = 1
                                         << 7, /* over temp wariing reported */
  DRV8323S_DRIVER_CONTROL_PWM_MODE_MASK = 0b11 << 5, /* PWM mode */
  DRV8323S_DRIVER_CONTROL_1PWM_COM_MASK = 1 << 4, /* 1PWM mode diode freewheel*/
  DRV8323S_DRIVER_CONTROL_1PWM_DIR_MASK = 1 << 3, /* 1PWM mode direction */
  DRV8323S_DRIVER_CONTROL_COAST_MASK = 1 << 2,    /* all FETs in Hi-Z */
  DRV8323S_DRIVER_CONTROL_BRAKE_MASK = 1 << 1,    /* all low FETs on */
  DRV8323S_DRIVER_CONTROL_CLR_FLT_MASK = 1 << 1,  /* clear latched fault bits */
};

enum /* 0x03 */ {
  DRV8323S_GATE_DRIVE_HS_LOCK_MASK = 0b111 << 8,        /* lock register */
  DRV8323S_GATE_DRIVE_HS_IDRIVEP_HS_MASK = 0b1111 << 4, /* HS positiv current */
  DRV8323S_GATE_DRIVE_HS_IDRIVEN_HS_MASK = 0b1111 << 0, /* HS negativ current */
};

enum /* 0x04 */ {
  DRV8323S_GATE_DRIVE_LS_CBC_MASK = 1 << 10,      /* cycle-by cycle operation */
  DRV8323S_GATE_DRIVE_LS_TDRIVE_MASK = 0b11 << 8, /* peak gate curr drive t*/
  DRV8323S_GATE_DRIVE_LS_IDRIVEP_LS_MASK = 0b1111 << 4, /* LS positiv current */
  DRV8323S_GATE_DRIVE_LS_IDRIVEN_LS_MASK = 0b1111 << 0, /* LS negativ current */
};

enum /* 0x05 */ {
  DRV8323S_OCP_CONTROL_TRETRY_MASK = 1 << 10, /* 0=4ms, 1=50us */
};

#endif /* _DRV8323S_H */
